There are many circuit designs which include circuit components, both active (such as transistors) and passive (such as resistors), which are required to be matched during their operation, over a temperature range. Where the circuits are constructed of discrete components, if necessary for optimizing system performance, adjustments typically must be made during the manufacturing process when assembling the circuits to insure component matching. This can be costly due to the labor required to make the adjustment for each manufactured circuit. Often times such adjustments provide correction only at the temperature at which the initial adjustment is made, which may not be satisfactory for other operational temperatures. In addition, some settings may be subject to shifts due to mechanical vibration. Implementing these circuits in integrated or monolithic form often necessarily requires the provision of external circuitry for providing these adjustments following the manufacture of the IC part, but does not overcome the above-noted problems.
For example, it is well known that the class of electronic gain control circuits, known as log-antilog electronic multipliers or VCAs (voltage controlled amplifiers), requires adjustment means (generally referred to as symmetry adjustment) to compensate for mismatches among the various transistors that implement the gain-control function. The requirement for such adjustment is mentioned in U.S. Pat. Nos. 3,714,462, and 4,403,199 issued to David E. Blackmer on Jan. 30, 1973 and Sep. 6, 1983 respectively; U.S. Pat. No. 4,234,804 issued to Gary Bergstrom on Nov. 18, 1980; U.S. Pat. No. 4,331,931 issued to Robert W. Adams on May 25, 1982; and U.S. Pat. Nos. 4,225,794 and 4,341,962 issued to Paul C. Buff on Sep. 30, 1980 and Jul. 27, 1982, respectively. This adjustment has historically been made via a potentiometer and associated fixed resistors, arranged to apply an adjustable potential to one or more of the bases of the transistors in the gain-control circuit. Such an adjustment method is costly due to the parts themselves, and the labor required to adjust the potentiometer during the manufacturing process of each circuit board. Further, such methods often yield a correction potential that is only correct at the temperature at which the initial adjustment was made. Finally, the potentiometer setting is subject to shifts due to mechanical vibration.
The most prevalent modern examples of such gain-control circuits are implemented in monolithic IC technology, which is well suited to these circuits as they require well-matched transistors that operate at substantially the same temperature. An example of a VCA is shown in FIG. 1.
The VCA shown in FIG. 1 includes an eight transistor cell. Eight transistor cell VCAs are known. See, for example, U.S. Pat. No. 4,331,931 issued to Robert W. Adams on May 25, 1982 and U.S. Pat. No. 4,341,962 issued to Paul C. Buff on Jul. 27, 1982. As shown in FIG. 1, an input information signal (e.g., an audio signal) I.sub.in is applied to the input terminal 10. Terminal 10 is connected to the collector of primary log (pnp) transistor Q.sub.3 and the collector of the primary log (npn) transistor Q.sub.5. The collectors of primary antilog transistors Q.sub.4 and Q.sub.6 (pnp and npn transistors respectively) are joined at junction 12 so as to form output terminal 14 for output current I.sub.out. One gain control signal is applied to the positive-sense gain-control port 16 as E.sub.cp, and to the negative-sense gain-control port 18 as E.sub.cn. The symmetry adjust signal E.sub.sym is applied to the symmetry port 22. As shown, the positive control signal input terminal 16 is connected to the base of the primary log transistor Q.sub.3, while the negative control signal input terminal 18 is connected to the base of primary log transistor Q.sub.5 and primary antilog transistor Q.sub.4. The emitter of each primary transistor Q.sub.3, Q.sub.4, Q.sub.5 and Q.sub.6 is connected to the emitter of a respective secondary transistor Q.sub.1, Q.sub.2, Q.sub.7 and Q.sub.8, with each secondary transistor being of a conductivity type opposite to that of the primary transistor to which it is connected. The bases and collectors of transistors Q.sub.1 and Q.sub.2 are tied together, and similarly the bases and collectors of transistors Q.sub.7 and Q.sub.8 are tied together. A voltage bias source V.sub.bias is connected between the bases and collectors of transistors Q.sub.1 and Q.sub.2 and the bases and collectors of transistors Q.sub.7 and Q.sub.8. In addition, the bases and collectors of transistors Q.sub.7 and Q.sub.8 are connected to a current source indicated as I.sub.power. The input terminal 10 is also connected to the inverting input of operational amplifier 20, with the non-inverting input connected to system ground and the output connected to the bases and collectors of transistors Q.sub.1 and Q.sub.2.
In general, because of the logarithmic relationship between base to emitter voltage V.sub.be and the collector current I.sub.c of a bipolar transistor, the log transistors will provide a voltage signal at the collectors of the secondary transistors which is proportional to the logarithm of the input current. The antilog transistors will provide the output current I.sub.out as a function of the antilogarithm of the voltage signal. Because the control voltage E.sub.c is applied to opposing polarities of both the log and antilog transistors, varying E.sub.c will vary the ratio of the output current I.sub.out to the input current I.sub.in. The symmetry adjustment signal, E.sub.sym, is applied to the symmetry adjust terminal 22. The requirement for symmetry adjustment arises from mismatches in the base-to-emitter voltage (V.sub.be)--collector current (I.sub.c characteristics among the log and antilog transistors in the gain-control circuit. This may be seen by observing FIG. 1 and the VCA transfer function: ##EQU1## wherein I.sub.out is the VCA output current;
I.sub.in is the VCA input current;
G is the nominal VCA current gain ##EQU2##
E.sub.cp is the potential applied to the positive-sense gain-control port;
E.sub.cn is the potential applied to the negative-sense gain-control port;
E.sub.sym is the potential applied to the symmetry port;
I.sub.b is the nominal bias current in the logging and anti-logging transistors when the gain-control circuit is set for unity gain; ##EQU3## is the "thermal voltage", a constant proportional to the absolute temperature (PTAT); and
I.sub.s1, through I.sub.s8 are the respective saturation currents for the logging and anti-logging transistors Q.sub.1 through Q.sub.8.
If all of the individual log/antilog pairs of transistors (Q.sub.1 /Q.sub.2, Q.sub.3 /Q.sub.4, Q.sub.5 /Q.sub.6, and Q.sub.7 /Q.sub.8) are identically matched for their V.sub.be -I.sub.c characteristics such that: EQU I.sub.s1 =I.sub.s2, I.sub.s3 =I.sub.s4, I.sub.s5 =I.sub.s6, and I.sub.s7 =I.sub.s8, (2)
and E.sub.sym is set to equal E.sub.cp, then equation (1) reduces to: EQU I.sub.out =GI.sub.in, (3)
which is the ideal case in which the output current is a linearly scaled version of the input current. In practice, however, there exist mismatches among the pairs of transistors, such that, without proper adjustment of the potential E.sub.sym, the output current will consist of, in addition to a scaled version of the input current, second harmonic distortion and gain-dependent dc offset components represented by the second term in equation (1) reproduced as follows: ##EQU4## These distortion and gain-dependent offset components are undesirable in high-quality audio applications, as well as other applications where a faithful scaled replica of an input signal is desired.
It is possible to properly adjust E.sub.sym to completely eliminate these undesirable components in the output signal. E.sub.sym must be adjusted such that the second term in equation (1) goes to zero. Thus, it is desirable that: ##EQU5## Solving for E.sub.sym : ##EQU6##
In practice the transistor matching achievable with modem IC processes is such that the desired E.sub.sym potential is no more than a few millivolts different from E.sub.cp with E.sub.cp typically being in the range of -700 to +400 millivolts. Thus, it is convenient to consider the difference between these two potentials: ##EQU7## as the desired adjustment potential. From the foregoing it can be seen that because V.sub.T is proportional to absolute temperature, the required E.sub.adj also must be proportional to absolute temperature (PTAT).
It should be noted that the circuit used in deriving the equations above is used for illustrative purposes. The effects of base currents, Early effect, and non-ideal log conformance due to finite ohmic base and emitter resistances in the logging and anti-logging transistors have been ignored for clarity. The techniques taught in U.S. Pat. No. 4,234,804 (Bergstrom) and U.S. Pat. No. 4,403,199 (Blackmer) to mitigate the effects of finite ohmic base and emitter resistances in the logging and anti-logging transistors are entirely compatible with the invention to be described, and in fact serve to bring the behavior of actual gain-control circuits closer to the ideal behavior of the simple circuit described in FIG. 1. The same is true of the technique taught in U.S. Pat. No. 4,454,433 (Welland) for mitigating the effects of Early effect mismatch among the log and antilog transistors. For gain-control circuits utilizing a cell of only four transistors, such as that described in U.S. Pat. No. 3,714,462 (Blackmet), it is easily shown that the required E.sub.adj is of the same form as that of equation (7) and that the present invention is equally applicable to such circuits.
In considering the prior art, as each gain control circuit is made it is not necessarily known whether E.sub.adj should be a positive voltage, or a negative voltage. The log transistors, as well as the antilog transistors, are matched as closely as possible so that any mismatching is necessarily unpredictable and random. This would suggest therefore that just as many circuits would require a positive E.sub.adj as would require a negative E.sub.adj. Accordingly, the source of E.sub.adj not only should include the means for adjusting the level of E.sub.adj in order to correct for V.sub.be -I.sub.c mismatches, but also for adjusting the polarity of E.sub.adj so that E.sub.adj can be made positive or negative. The most common prior art approach for adjusting E.sub.adj to the desired polarity and value is illustrated in FIG. 2. A resistor R.sub.1 is connected between the bases of antilog transistor Q.sub.6 and log transistor Q.sub.3, and a resistor R.sub.2 is connected between the base of transistor Q.sub.6 and the wiper of a potentiometer R.sub.3. The ends of potentiometer R.sub.3 are connected between potentials V.sub.pos and V.sub.neg (typically, but not necessarily, equal and opposite voltages) to create a variable potential at the wiper. The values of these components are typically chosen such that the resistance of R.sub.2 is much larger than the resistance of R.sub.3, and the ratio of R.sub.2 to R.sub.1 is chosen to restrict the range of voltages across R.sub.1, to the few millivolts necessary to correctly adjust the VCA symmetry. Further, R.sub.1 is typically chosen to be less than 100 ohms so as not to add excessively to the base resistance of antilog transistor Q.sub.6. Finally, E.sub.cp is typically driven by a very low-impedance voltage source. Under these conditions E.sub.sym may be approximated by: ##EQU8## where V.sub.wiper is the voltage at the wiper of R.sub.3. The net adjustment voltage E.sub.adj developed across R.sub.1 will be: ##EQU9##
The symmetry adjustment is typically made with E.sub.cp and E.sub.cn both set to 0 volts so that the current gain of the VCA is unity. As can be seen from equation (9), if the positive-sense gain control port 16 is then used for adjusting the gain of the VCA, either in conjunction with or instead of the negative-sense gain control port 18, the E.sub.adj potential will deviate from the desired value as the E.sub.cp potential is varied. This leads to degraded distortion and offset-versus-gain performance at gains other than unity.
When this technique is implemented using discrete components for R.sub.1, R.sub.2, and R.sub.3, approximate temperature compensation of the E.sub.adj potential can be achieved by using a temperature-dependent resistor for R.sub.1. If R.sub.2 is much larger than R.sub.1 (which is typically the case) and R.sub.1 's value varies 0.33% for every one degree centigrade variation from room temperature while R.sub.2 's value remains fixed, then E.sub.adj will vary approximately PTAT fashion. Of course, it is difficult to ensure that the discrete resistor stays at exactly the same temperature as transistors Q.sub.1 through Q.sub.2. While integrating the resistors onto the same IC with the transistors might solve this problem, it is difficult with current IC technology to fabricate integrated resistors with specific, well-controlled temperature coefficients.